tm september 2008 FDMA1027PT dual p-ch annel powertrench ? mosfet ?2008 fairchild semiconductor corporation FDMA1027PT rev.b1 www.fairchildsemi.com 1 FDMA1027PT dual p-channel powertrench ? mosfet ? 20 v, ?3 a, 120 m ? features ? max r ds(on) = 120 m ? at v gs = -4.5 v, i d = -3.0 a ? max r ds(on) = 160 m ? at v gs = -2.5 v, i d = -2.5 a ? max r ds(on) = 240 m ? at v gs = -1.8 v, i d = -1.0 a ? low profile - 0.55 mm maximum - in the new package microfet 2x2 thin ? rohs compliant general description this device is designed specifically as a single package solution for the battery charge switch in cellular handset and other ultra-portable applications. it features two independent p-channel mosfets with low on- state resistance for minimum conduction losses. when connec ted in the typical common source configuration, bi-directi onal current flow is possible. the microfet 2x2 thin package offers exceptional thermal performance for it's physical size and is well suited to linear mode applications. applications ? battery management ? load switch ? battery protection microfet 2x2 thin 1 6 5 2 4 3 s1 g1 d2 d1 g2 s2 s2 g2 d1 d2 g1 s1 pin 1 d1 d2 1 3 2 6 5 4 mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage -20 v v gs gate to source voltage 8 v i d drain current -continuous t a = 25 c (note 1a) -3 a -pulsed -6 p d power dissipation for single operation t a = 25 c (note 1a) 1.4 w power dissipation for single operation t a = 25 c (note 1b) 0.7 t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient (single o peration) (note 1a) 86 c/w r ja thermal resistance, junction to ambient (single o peration) (note 1b) 173 r ja thermal resistance, junction to ambient (dual operation) 69 r ja thermal resistance, junction to ambient (dual operation) 151 device marking device package reel size tape width quantity 27 FDMA1027PT microfet 2x2 thin 7 ?? 8 mm 3000 units
FDMA1027PT dual p-ch annel powertrench ? mosfet www.fairchildsemi.com 2 ?2008 fairchild semiconductor corporation FDMA1027PT rev.b1 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = -250 a, v gs = 0 v -20 v ? bv dss ? t j breakdown voltage temperature coefficient i d = -250 a, referenced to 25 c -12 mv / c i dss zero gate voltage drain current v ds = -16 v, v gs = 0 v -1 a i gss gate to source leakage current v gs = 8 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = -250 a -0.4 -0.7 -1.3 v ? v gs(th) ? t j gate to source threshold voltage temperature coefficient i d = -250 a, referenced to 25 c 2 mv/c r ds(on) drain to source on resistance v gs = -4.5 v, i d = -3.0 a 90 120 m ? v gs = -2.5 v, i d = -2.5 a 120 160 v gs = -1.8 v, i d = -1.0 a 172 240 v gs = -4.5 v, i d = -3.0 a , t j = 125 c 118 160 i d(on) on to state drain current v gs = -4.5 v, v ds = -5 v -20 a g fs forward transconductance v ds = -5 v, i d = -3.0 a 7 s c iss input capacitance v ds = -10 v, v gs = 0 v, f = 1 mhz 435 pf c oss output capacitance 80 pf c rss reverse transfer capacitance 45 pf t d(on) turn-on delay time v dd = -10 v, i d = -1.0 a v gs = -4.5 v, r gen = 6 ? 918ns t r rise time 11 19 ns t d(off) turn-off delay time 15 27 ns t f fall time 612ns q g total gate charge v dd = -10 v, i d = -3.0 a v gs = -4.5 v 46nc q gs gate to source gate charge 0.8 nc q gd gate to drain ?miller? charge 0.9 nc i s maximum continuous drain-source diode forward current -1.1 a v sd source to drain diode forward voltage v gs = 0 v, i s = -1.1 a (note 2) -0.8 -1.2 v t rr reverse recovery time i f = -3.0 a, di/dt = 100 a/ s 17 ns q rr reverse recovery charge 6 nc notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 30 0 s, duty cycle < 2.0%. a. 86 c/w when mounted on a 1 in 2 pad of 2 oz copper. b. 173 c/w when mounted on a minimum pad of 2 oz copper.
FDMA1027PT dual p-ch annel powertrench ? mosfet www.fairchildsemi.com 3 ?2008 fairchild semiconductor corporation FDMA1027PT rev.b1 typical characteristics t j = 25 c unless otherwise noted figure 1. 0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5 6 v gs = -3 v v gs = -3.5 v -v ds , drain to source voltage (v) -i d , drain current (a) v gs = -1.8 v v gs = -2.5 v pulse duration = 300 p s duty cycle = 2% max v gs = -2 v v gs = -1.5 v v gs = -4.5 v on region characteristics figure 2. 0123456 0.5 1.0 1.5 2.0 2.5 3.0 v gs = -3.5 v v gs = -2.5 v v gs = -1.8 v pulse duration = 300 p s duty cycle = 2%max normalized drain to source on-resistance -i d , drain current (a) v gs = -2 v v gs = -3 v v gs = -1.5 v v gs = -4.5 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -50 -25 0 25 50 75 100 125 150 0.8 0.9 1.0 1.1 1.2 1.3 1.4 i d = -3 a v gs = -4.5 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 0246810 0.04 0.08 0.12 0.16 0.20 0.24 0.28 t j = 125 o c i d = -1.5 a t j = 25 o c -v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( : ) pulse duration = 300 p s duty cycle = 2% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5 6 -v gs , gate to source voltage (v) -i d , drain current (a) t j = 125 o c v ds = -5 v pulse duration = 300 p s duty cycle = 2% max t j = -55 o c t j = 25 o c figure 6. 0 0.2 0.4 0.6 0.8 1.0 1.2 0.0001 0.001 0.01 0.1 1 10 t j = -55 o c t j = 25 o c t j = 125 o c v gs = 0 v -i s , reverse drain current (a) -v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMA1027PT dual p-ch annel powertrench ? mosfet www.fairchildsemi.com 4 ?2008 fairchild semiconductor corporation FDMA1027PT rev.b1 figure 7. 012345 0 1 2 3 4 5 q g , gate charge (nc) -v gs , gate to source voltage (v) i d = -3 a v dd = -10 v v dd = -15 v v dd = -5 v gate charge characteristics figure 8. 048121620 0 100 200 300 400 500 600 700 f = 1 mhz v gs = 0 v capacitance (pf) -v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage f i g u r e 9 . f o r w a r d b i a s s a f e operating area 0.1 1 10 100 0.01 0.1 1 10 100 100 us 10 s 1 s dc 100 ms 10 ms 1 ms -i d , drain current (a) -v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 173 o c/w t a = 25 o c figure 10. 10 -4 10 -3 10 -2 10 -1 110 100 1000 1 10 100 1000 single pulse r t ja = 173 o c/w t a = 25 o c v gs = -10 v p ( pk ) , peak transient power (w) t, pulse width (sec) 0.2 s i n g l e p u l s e m a x i m u m p o w e r d i s s i p a t i o n figure 11. 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.01 0.1 1 single pulse r t ja = 173 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to-ambient transient thermal response curve typical characteristics t j = 25 c unless otherwise noted
FDMA1027PT dual p-ch annel powertrench ? mosfet www.fairchildsemi.com 5 ?2008 fairchild semiconductor corporation FDMA1027PT rev.b1 dimensional outlin e and pad layout
www.fairchildsemi.com 6 FDMA1027PT dual p-channel powertrench ? mosfet ?2008 fairchild semiconductor corporation FDMA1027PT rev.b1 rev. i36 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. * ezswitch? and flashwriter ? are trademarks of system general corporati on, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fai rchild semiconductor corporation. as used herein: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms build it now? 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